1. Field of the Invention
The present invention relates generally to bus architectures in personal computer systems. More particularly, the present invention relates to the manner and techniques by which components in a computer system communicate over a serial bus. Still more particularly, the invention relates to an improved technique for upgrading serial bus functionality without changing the serial bus protocol.
2. Background of the Invention
A personal computer system includes a number of modular components with specialized functions that cooperatively interact to realize the many features of modern computer systems. The ability of these various components to exchange data and other information is vital to the successful operation of a computer system. One of the critical requirements in designing a new computer system is that all system components (including those that may be added to the system by a user) must be compatible. A component is compatible if it effectively communicates and transfers data without interfering or contending with the operation of other system components. Thus, designing an improved computer system requires that any features added to existing components conform to the data transfer protocols of the previous design.
As an example, some of the early computer systems included a processor (or CPU), random access memory (RAM), and certain peripheral devices such as a floppy drive, a keyboard and a display. These components typically were coupled together using a network of address, data and control lines, commonly referred to as a "bus." As computer technology evolved, it became common to connect additional peripheral devices to the computer through ports (such as a parallel port or a serial port), or by including the peripheral device on the main system circuit board (or "motherboard") and connecting it to the system bus. One early bus that still is in use today is the Industry Standard Architecture (ISA) bus. The ISA bus, as the name implies, was a bus standard adopted by computer manufacturers to permit the manufacturers of peripheral devices to design devices that would be compatible with most computer systems. The ISA bus includes 16 data lines and 24 address lines and operates at a clock speed of 8 MHz. A large number of peripheral components have been developed over the years to operate with the ISA protocol.
The components which connect to a given bus receive data from the other components on the same bus via the bus signal lines. Selected components may operate as "bus masters" to initiate data transfers over the bus. Each component on the bus circuit operates according to a protocol associated with that bus which defines the purpose of each bus signal and regulates such parameters as bus speed and arbitration between components requesting bus mastership. A bus protocol also determines the proper sequence of bus signals for transferring data over the bus. As computer systems have continued to evolve, new bus circuits offering heightened functionality have replaced older bus circuits, allowing existing components to transfer data more effectively.
One way in which the system bus has been made more effective is to permit data to be exchanged in a computer system without the assistance of the CPU. To implement this design, a new bus architecture called Extended Industrial Standard Architecture (EISA) was developed. The EISA bus protocol permits system components residing on the EISA bus to obtain mastership of the bus and to run cycles on the bus independently of the CPU. Another bus that has become increasingly popular is the Peripheral Component Interconnect (PCI) bus. Like the EISA bus, the PCI bus provides bus master capabilities to devices connected to the PCI bus. The PCI bus also operates at clock speeds of 33 MHz or faster. Current designs contemplate implementing a 100 MHz PCI bus.
To ensure that existing components continue to remain compatible with future generations of computer systems, new computer designs often include many different types of buses. Because different buses operate according to different protocols, the computer design uses bridge devices to interface, or bridge, the different buses. Such a scheme permits components coupled to one bus to exchange data with components coupled to another bus.
For example, FIG. 1 illustrates a representative prior art computer system that includes a CPU coupled to a bridge logic device via a CPU bus. The bridge logic device is sometimes referred to as a "North bridge" for no other reason than it often is depicted at the upper end of a computer system drawing. The North bridge also couples to the main memory array by a memory bus. The North bridge couples the CPU and memory to the peripheral devices in the system through a PCI bus or other expansion bus (such as an EISA bus). Various components that understand PCI protocol may reside on the PCI bus, such as a graphics controller.
If other secondary expansion buses are provided in the computer system, another bridge logic device typically is used to couple the PCI bus to that expansion bus. This bridge logic is sometimes referred to as a "South bridge" reflecting its location vis-a-vis the North bridge in a typical computer system drawing. An example of such bridge logic is described in U.S. Pat. No. 5,634,073, assigned to Compaq Computer Corporation. In FIG. 1, the South bridge couples the PCI bus to an ISA bus. Various ISA-compatible devices are shown coupled to the ISA bus.
The South bridge may also support an input/output (I/O) controller that interfaces to basic input/output devices such as a keyboard, a mouse, a floppy disk drive, and various input switches such as a power switch and a suspend switch. The I/O controller typically couples to the South bridge via a standard bus, shown as an ISA bus in FIG. 1. A serial bus, which generally is a bus with only one data signal, may provide an additional connection between the I/O controller and South bridge. The I/O controller typically comprises an ISA bus interface (not specifically shown) and transmit and receive registers (not specifically shown) for exchanging data with the South bridge over the serial bus. The I/O controller generally has the capability to handle power management functions such as reducing or terminating power to components such as the floppy drive, blocking the clock signals that drive components such as the bridge devices and CPU, and inducing sleep mode in the peripheral buses. The I/O controller further asserts System Management Interrupt (SMI) signals to various devices such as the CPU and North bridge to indicate special conditions pertaining to input/output activities such as sleep mode. The I/O controller typically incorporates a counter or a Real Time Clock (RTC) to track the activities of certain components such as the hard drive and the PCI bus, inducing a sleep mode or reduced power mode after a predetermined time of inactivity. The I/O controller may also induce a low-power suspend mode if the suspend switch is pressed, in which the power is completely shut off to all devices except the I/O controller itself.
In one particular computer design, the serial bus connecting the South bridge and I/O controller comprises an eight-bit serial bus in which eight bits of data are transmitted sequentially over the bus. The data exchanged over the serial bus generally represents power management status and other configuration data. The I/O controller and South bridge each include transmit and receive registers coupled to the serial bus. The transmit register in the I/O controller holds data to be transmitted to the receive register in the South bridge, while the transmit register in the South bridge holds data to be sent to the receive register in the I/O controller. Each data bit sent by the I/O controller represents the state of a certain variable or situation, such as whether a sleep request or idle request is asserted or whether the ISA bus pins should be tristated for power-down mode. Data bits transmitted from the South bridge to the I/O controller are defined to represent similar information, such as whether the processor clock is disabled for suspend mode or whether the PCI bus is active.
If one of the status values in the I/O controller changes, the I/O controller may drive the serial bus low to request an exchange of data with the South bridge over the serial bus. The South bridge may also request an exchange of data with the I/O controller by driving the serial bus low. In response to either device driving the serial bus low, the I/O controller first transmits all eight of its status bits to the South bridge, one bit at a time. The South bridge follows by consecutively transmitting each of its eight status bits to the I/O controller. In this manner, the I/O controller and South bridge exchange a total of sixteen status values.
Recently, some computer developers have adopted the Advanced Configuration and Power Interface (ACPI) as a power management specification for new computer designs. The ACPI specification allows the computer operating system software to control the amount of power delivered to the various computer components. Because conforming to the ACPI specification requires that both the I/O controller and South bridge transmit more than eight different status bits, however, the serial bus architecture described above is not adequate to support the ACPI features. Upgrading the functionality of such a serial bus to include ACPI conformance, however, will require significant and, perhaps, costly design modifications to both the I/O controller and South bridge chip. It thus would be advantageous to transmit more than eight bits of data across the serial bus with as little design impact to the existing bus as possible.
Despite the apparent advantages of continuing to increase computer system functionality as user needs evolve, modifications to existing components can be prohibitively costly and can limit backward-compatibility. To date, no one has designed a computer system to transmit more than eight bits of information on an eight-bit serial bus.